The present invention relates, in general, to semiconductor manufacturing and, more particularly, to abrasive particles used to clean semiconductor wafers during chemical mechanical planarization.
Semiconductor devices are widely and commonly used in the construction of electronic circuits for many types of electronic products. The manufacturing of a semiconductor device typically involves growing a cylindrical-shaped silicon (or other base semiconductive material) ingot. The ingot is sliced into circular flat wafers. Through a number of thermal, chemical, and physical manufacturing processes, active semiconductor devices and passive devices are formed on one or both surfaces of the wafer. The wafer is cut into individual rectangular semiconductor die which are then mounted and attached to a leadframe, encapsulated, and packaged as discrete or integrated circuits. The packaged discrete and integrated circuits are mounted to a printed circuit board and interconnected to perform the desired electrical function.
One of the processes involved in the manufacture of the semiconductor wafer is a step known as chemical mechanical planarization or polish (CMP). The CMP process uses chemical reactions and mechanical buffing to remove excess material left on the surface of the wafer following formation of the active and passive devices, or during the interconnection of these devices. A slurry of abrasive particles, such as alumina, silica, or ceria particles, are suspended in a fluid, such as an aqueous solution or liquid or supercritical carbon dioxide, which contains additives that induce chemical changes on the wafer surface, including oxidation, dissolution, and passivation, or which may inhibit chemical changes on the wafer surface. Aqueous slurries may be acidic or basic in nature. The slurries are deposited on the surface of a polishing pad. The slurry chemically modifies the wafer surface. The mechanical buffing action removes the modified surface layer, as well as bulk material, including the removal of high points on the surface of the wafer. Following polishing, particles, which may have originated from the slurry, from the layers being polished, from the backside of the wafer, from the CMP apparatus, on the walls of a deposition chamber, on the walls of an etch chamber, or from a photoresist process, can be left on the wafer. In order to achieve extreme flatness on the wafer surface, the CMP process must exercise precise control over the polishing time, pressure of the wafer against the pad, pad-wafer relative velocity, slurry particle size, slurry feed rate, and composition of the slurry. The wafer receives a post-CMP cleaning process to remove as many particles as possible from the surface of the wafer. The cleaning process may involve wafer rotation, liquid cleaning solutions, supercritical fluids, ultrasonic or megasonic energy, brushes, laser energy, or particles of frozen gas.
Any particles that remain on the wafer surface following the CMP and cleaning processes can cause defects in the integrated circuit die. The particles that remain may be pieces of wafer material which did not get removed by the CMP and cleaning processes. The particles that remain may also be pieces of the abrasive particles used in the CMP slurry that broke off during the mechanical buffing, or were otherwise left behind following CMP and cleaning, or they may originate on the walls of the vessels that process the wafers. The primary particles of interest are the left over slurry particles following CMP.
In the semiconductor industry, manufacturers must address a significant concern of particle contamination on semiconductor wafers and integrated circuits. In general, a particle that is one-third the critical line width of the relevant technology can cause a defect and reduce production yield. The critical line width refers to the minimum construction geometry in the relevant technology. In some cases, the minimum construction geometry refers to a minimum effective gate width of a metal oxide semiconductor (MOS) transistor. In other cases, the minimum construction geometry refers to the width of a trench used in device interconnection.
In silicon-based technology for example, the present critical line width is approximately 0.25 microns. Work is under way to reduce that critical line width to 0.08-0.13 microns. The semiconductor industry has been and will continue to reduce the critical line width for all technologies in order to increase device density and electrical functions available for a given surface area of the die.
Any particle adhering to or left on the semiconductor wafer or integrated circuit die after the manufacturing process which approaches a size of about one-third of the critical line width, e.g. particles as small as 0.08 microns for 0.25 micron technology, can cause product contamination or a defect in the end device.
Although the contamination particles remaining after the CMP process do not adhere strongly to the surface of the wafer, the particles are so small that it is difficult to apply the necessary force to remove them. In the cleaning process following CMP where the wafer is flushed with a cleansing solution, the particles are so small and close to the wafer surface that the solution cannot assert much force to dislodge the contaminants. The use of cleaning brushes can damage the surface of the wafer and hydroplane over the top of the particles.
In one embodiment, the present invention is a slurry solution for chemical mechanical planarization (CMP) of a semiconductor wafer comprising an abrasive particle having a central body and a plurality of extensions from the central body of the abrasive particle. At least one of the plurality of extensions holds a center of mass of the abrasive particle a distance from the semiconductor wafer.
In another embodiment, the present invention is a method of manufacturing a semiconductor wafer, comprising providing a chemical mechanical planarization (CMP) on the semiconductor wafer with a slurry solution comprising an abrasive particle having a central body and a plurality of extensions from the central body of the abrasive particle. At least one of the plurality of extensions holds a center of mass of the abrasive particle a distance from the semiconductor wafer.